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rev.0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD9744 * one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 14-bit, 165 msps txdac d/a converter functional block diagram 150pf +1.20v ref avdd acom reflo current source array 3.3v segmented switches lsb switches refio fs adj dvdd dcom clock 3.3v r set 0.1 f clock iouta ioutb latches AD9744 sleep digital data inputs (db13?db0) mode features high-performance member of pin-compatible txdac product family excellent spurious-free dynamic range performance sfdr to nyquist: 83 dbc @ 5 mhz output 80 dbc @ 10 mhz output 73 dbc @ 20 mhz output snr @ 5 mhz output, 125 msps: 77 db twos complement or straight binary data format differential current outputs: 2 ma to 20 ma power dissipation: 135 mw @ 3.3 v power-down mode: 15 mw @ 3.3 v on-chip 1.20 v reference cmos-compatible digital interface package: 28-lead soic and tssop packages edge-triggered latches applications wideband communication transmit channel: direct if base stations wireless local loop digital radio link direct digital synthesis (dds) instrumentation product description the AD9744 is a 14-bit resolution, wideband, third generation member of the txdac series of high-performance, low power cmos digital-to-analog converters (dacs). the txdac family, consisting of pin-compatible 8-, 10-, 12-, and 14-bit dacs, is specifically optimized for the transmit signal path of communica- tion systems. all of the devices share the same interface options, small outline package, and pinout, providing an upward or down- ward component selection path based on performance, resolution, and cost. the AD9744 offers exceptional ac and dc performance while supporting update rates up to 165 msps. the AD9744? low power dissipation makes it well suited for portable and low power applications. its power dissipation can be further reduced to a mere 60 mw with a slight degradation in performance by lowering the full-scale current output. also, a power-down mode reduces the standby power dissipation to approximately 15 mw. a segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. edge- triggered input latches and a 1.2 v temperature compensated band gap reference have been integrated to provide a complete monolithic dac solution. the digital inputs support 3 v cmos logic families. product highlights 1. the AD9744 is the 14-bit member of the pin-compatible txdac family that offers excellent inl and dnl performance. 2. data input supports two? complement or straight binary data coding. 3. high-speed, single-ended cmos clock input supports 165 msps conversion rate. 4. low power: complete cmos dac function operates on 135 mw from a 3.0 v to 3.6 v single supply. the dac full-scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. 5. on-chip voltage reference: the AD9744 includes a 1.2 v temperature-compensated band gap voltage reference. 6. industry standard 28-lead soic and tssop packages. txdac is a registered trademark of analog devices, inc. * protected by u.s. patent numbers 5568145, 5689257, and 5703519.
rev. 0 ?2? AD9744 dc specifications parameter min typ max unit resolution 14 bits dc accuracy 1 integral linearity error (inl) e5 0.8 +5 lsb differential nonlinearity (dnl) e3 0.5 +3 lsb analog output offset error e0.02 +0.02 % of fsr gain error (without internal reference) e0.5 0.1 +0.5 % of fsr gain error (with internal reference) e0.5 0.1 +0.5 % of fsr full-scale output current 2 2.0 20.0 ma output compliance range e1.0 +1.25 v output resistance 100 k w output capacitance 5 pf reference output reference voltage 1.14 1.20 1.26 v reference output current 3 100 na reference input input compliance range 0.1 1.25 v reference input resistance (ext. ref) 1 m w small signal bandwidth 0.5 mhz temperature coefficients offset drift 0 ppm of fsr/ 50 ppm of fsr/ 100 ppm of fsr/ 50 ppm/ w r load at iouta and ioutb, f clock = 100 msps and f out = 40 mhz. 6 5% power supply variation. specifications subject to change without notice. (t min to t max , avdd = 3.3 v, dvdd = 3.3 v, i outfs = 20 ma, unless otherwise noted.) -specifications
rev. 0 ?3? AD9744 parameter min typ max unit dynamic performance maximum output update rate (f clock ) 165 msps output settling time (t st ) (to 0.1%) 1 11 ns output propagation delay (t pd )1ns glitch impulse 5 pv-s output rise time (10% to 90%) 1 2.5 ns output fall time (10% to 90%) 1 2.5 ns output noise (i outfs = 20 ma) 2 50 pa/ hz hz hz hz hz hz hz hz hz hz hz hzhz hzhz hzhz hzhz h hz hz hz hz hz hz hz hz hz hz hz hzhz w load. 2 output noise is measured with a full-scale output set to 20 ma with no conversion activity. it is a measure of the thermal nois e only. 3 noise spectral density is the average noise power normalized to a 1 hz bandwidth, with the dac converting and producing an outp ut tone. specifications subject to change without notice. dynamic specifications (t min to t max , avdd = 3.3 v, dvdd = 3.3 v, i outfs = 20 ma, differential transformer coupled output, 50 doubly terminated, unless otherwise noted.)
rev. 0 ?4? AD9744 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD9744 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings * with parameter respect to min max unit avdd acom e0.3 +3.9 v dvdd dcom e0.3 +3.9 v acom dcom e0.3 +0.3 v avdd dvdd e3.9 +3.9 v clock, sleep dcom e0.3 dvdd + 0.3 v digital inputs dcom e0.3 dvdd + 0.3 v iouta, ioutb acom e1.0 avdd + 0.3 v refio, reflo, fsadj acom e0.3 avdd + 0.3 v junction temperature 150 ja = 71.4 ja = 97.9 m a logic 0 current e10 +10 m a input capacitance 5 pf input setup time (t s ) 2.0 ns input hold time (t h ) 1.5 ns latch pulsewidth (t lpw ) 1.5 ns (t min to t max , avdd = 3.3 v, dvdd = 3.3 v, i outfs = 20 ma, unless otherwise noted.)
rev. 0 AD9744 ?5? pin configuration 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) 28 27 26 25 24 23 22 21 AD9744 nc = no connect db9 db8 db7 db6 db5 db4 db3 db2 db1 (lsb) db0 clock dvdd dcom mode avdd reserved iouta ioutb acom nc fs adj refio reflo sleep db10 db11 db12 (msb) db13 pin function descriptions pin no. mnemonic description 1 db13 most significant data bit (msb) 2e13 db12edb1 data bits 12-1 14 db0 least significant data bit (lsb) 15 sleep power-down control input. active high. contains active pull-down circuit; it may be left unterminated if not used. 16 reflo reference ground when internal 1.2 v reference used. connect to avdd to disable internal reference. 17 refio reference input/output. serves as reference input when internal reference disabled (i.e., tie reflo to avdd). serves as 1.2 v reference output when internal reference activated (i.e., tie reflo to agnd). requires 0.1 m f capacitor to agnd when internal reference activated. 18 fs adj full-scale current output adjust 19 nc no internal connection 20 acom analog common 21 ioutb complementary dac current output. full-scale current when all data bits are 0s. 22 iouta dac current output. full-scale current when all data bits are 1s. 23 reserved reserved. do not connect to common or supply. 24 avdd analog supply voltage (3.3 v) 25 mode selects input data format. connect to dgnd for straight binary, dvdd for two?s complement 26 dcom digital common 27 dvdd digital supply voltage (3.3 v) 28 clock clock input. data latched on positive edge of clock.
rev. 0 AD9744 ?6? definitions of specifications linearity error (also called integral nonlinearity or inl) linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. differential nonlinearity (or dnl) dnl is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. monotonicity a d/a converter is monotonic if the output either increases or remains constant as the digital input increases. offset error the deviation of the output current from the ideal of zero is called the offset error. for iouta, 0 ma output is expected when the inputs are all 0s. for ioutb, 0 ma output is expected when all inputs are set to 1s. gain error the difference between the actual and ideal output span. the actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. output compliance range the range of allowable voltage at the output of a current output dac. operation beyond the maximum compliance limits may cause either output stage saturation or breakdown resulting in nonlinear performance. temperature drift temperature drift is specified as the maximum change from the ambient (25
rev. 0 ?7? t ypical performance characteristicseAD9744 f out ? mhz sfdr ? dbc 45 110100 65msps 125msps 165msps 50 55 60 65 70 75 80 85 90 95 tpc 1. sfdr vs. f out @ 0 dbfs 060 10 45 50 55 60 65 70 75 80 85 90 95 f out ? mhz sfdr ? dbc 40 30 20 50 0dbfs ?12dbfs ?6dbfs tpc 4. sfdr vs. f out @ 165 msps ?20 ?15 ?25 ?10 ?5 0 a out ? dbfs sfdr ? dbc 45 50 55 60 65 70 75 80 85 90 95 65msps 125msps 165msps tpc 7. single-tone sfdr vs. a out @ f out = f clock /5 05 25 10 15 20 45 50 55 60 65 70 75 80 85 90 95 0dbfs ?6dbfs f out ? mhz sfdr ? dbc ?12dbfs tpc 2. sfdr vs. f out @ 65 msps 05 25 10 15 20 45 50 55 60 65 70 75 80 85 90 95 f out ? mhz sfdr ? dbc 20ma 10ma 5ma tpc 5. sfdr vs. f out and i outfs @ 65 msps and 0 dbfs 90 110 70 130 150 170 60 65 70 75 85 90 20ma f clock ? msps snr ? db 10ma 5ma 50 80 tpc 8. snr vs. f clock and i outfs @ f out = 5 mhz and 0 dbfs 05 45 10 15 35 45 50 55 60 65 70 75 80 85 90 95 0dbfs ?6dbfs ?12dbfs f out ? mhz sfdr ? dbc 40 30 20 25 tpc 3. sfdr vs. f out @ 125 msps 45 50 55 60 65 70 75 80 85 90 95 sfdr ? dbc 0 ?5 ?25 ?10 ?15 ?20 a out ? dbfs 65msps 125msps 165msps tpc 6. single-tone sfdr vs. a out @ f out = f clock /11 0 ?5 ?25 ?10 ?15 ?20 45 50 55 60 65 70 75 80 85 90 95 a out ? dbfs sfdr ? dbc 65msps (8.3,10.3) 78msps (10.1, 12.1) 125msps (16.9, 18.9) 165msps (22.6, 24.6) tpc 9. dual-tone imd vs. a out @ f out = f clock /7
rev. 0 AD9744 ?8? 4096 8192 12288 16384 ?1.0 ?0.5 0 0.5 1.0 code error ? lsb 0 ?1.5 1.5 tpc 10. typical inl 16 26 11 16 21 ?100 frequency ? mhz magnitude ? dbm 31 f clock = 78msps f out = 15.0mhz sfdr = 79dbc amplitude = 0dbfs 36 ?90 ?80 ?70 ?60 ?50 ?40 ?20 0 ?10 ?30 tpc 13. single-tone sfdr center 33.22mhz ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?40 ?20 ?30 ?50 3mhz span 30mhz cu1 c0 c0 c11 c11 c12 c12 cu1 cu2 cu2 ?39.01dbm 29.38000000mhz ch pwr ?19.26dbm acp up ?64.98db acp lo w +0.55db alt1 up ?66.26db alt1 low ?64.23db magnitude ? dbm tpc 16. two-carrier umts spectrum (aclr = 64 db) 0 4096 1.0 0.8 ?0.6 0.4 0.2 0 code error ? lsb ?0.2 ?1.0 ?0.8 ?0.4 0.6 8192 12288 16384 tpc 11. typical dnl 16 26 11 16 21 ?100 frequency ? mhz magnitude ? dbm 31 f clock = 78msps f out1 = 15.0mhz f out2 = 15.4mhz sfdr = 77dbc amplitude = 0dbfs 36 ?90 ?80 ?70 ?60 ?50 ?40 ?20 0 ?10 ?30 tpc 14. dual-tone sfdr ?40 ?20 60 02040 50 55 60 65 70 75 80 85 90 4mhz 19mhz 34mhz temperature ? c sfdr ? dbc 80 49mhz 95 45 tpc 12. sfdr vs. temperature @ 165 msps, 0 dbfs 16 26 11 16 21 ?100 frequency ? mhz magnitude ? dbm 31 f clock = 78msps f out1 = 15.0mhz f out2 = 15.4mhz f out3 = 15.8mhz f out4 = 16.2mhz sfdr = 75dbc amplitude = 0dbfs 36 ?90 ?80 ?70 ?60 ?50 ?40 ?20 0 ?10 ?30 tpc 15. four-tone sfdr
rev. 0 AD9744 ?9? functional description figure 3 shows a simplified block diagram of the AD9744. the AD9744 consists of a dac, digital control logic, and full-scale output current control. the dac contains a pmos current source array capable of providing up to 20 ma of full-scale current (i outfs ). the array is divided into 31 equal currents that make up the five most significant bits (msbs). the next four bits, or middle bits, consist of 15 equal current sources whose value is 1/16th of an msb current source. the remaining lsbs are binary weighted fractions of the middle bits current sources. implementing the middle and lower bits with current sources, instead of an r-2r ladder, enhances its dynamic perfor- mance for multitone or low amplitude signals and helps maintain the dac?s high output impedance (i.e., >100 k w ). all of these current sources are switched to one or the other of the two output nodes (i.e., iouta or ioutb) via pmos differential current switches. the switches are based on the architecture that was pioneered in the ad9764 family, with further refinements to reduce distortion contributed by the switching transient. this switch architecture also reduces vari- ous timing errors and provides matching complementary drive signals to the inputs of the differential current switches. the analog and digital sections of the AD9744 have separate power supply inputs (i.e., avdd and dvdd) that can operate independently over a 3.0 v to 3.6 v range. the digital section, which is capable of operating up to a 165 msps clock rate, consists of edge-triggered latches and segment decoding logic circuitry. the analog section includes the pmos current sources, the associated differential switches, a 1.2 v band gap voltage reference, and a reference control amplifier. the dac full-scale output current is regulated by the refer- ence control amplifier and can be set from 2 ma to 20 ma via an external resistor, r set , connected to the full-scale adjust (fsadj) pin. the external resistor, in combination with both the reference control amplifier and voltage reference v refio , sets the reference current i ref , which is replicated to the segmented current sources with the proper scaling factor. the full-scale current, i outfs , is 32 times i ref . reference operation the AD9744 contains an internal 1.2 v band gap reference. the internal reference can be disabled by raising reflo to avdd. it can also be easily overridden by an external reference with no effect on performance. refio serves as either an input or output depending on whether the internal or an external reference is used. to use the internal reference, simply decouple the refio pin to acom with a 0.1 m f capacitor and connect reflo to acom via a resistance less than 5 w . the internal reference voltage will be present at refio. if the voltage at refio is to be used anywhere else in the circuit, an external buffer amplifier with an input bias current of less than 100 na should be used. an example of the use of the internal reference is given in fig ure 4. 150pf +1.2v ref avdd reflo current source array 3.3v refio fs adj 2k 0.1 f AD9744 additional load optional external ref buffer figure 4. internal reference configuration an external reference can be applied to refio as shown in figure 5. the external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. note that the 0.1 m f compensation capacitor is not required since the internal refer- ence is overridden, and the relatively high input impedance of refio minimizes any loading of the external reference. 150pf +1.2v ref avdd reflo current source array 3.3v refio fs adj r set AD9744 external ref i ref = v refio /r set avdd reference control amplifier v refio figure 5. external reference configuration digital data inputs ( db13?db0 ) 150pf +1.20v ref avdd acom reflo pmos current source array 3.3v segmented switches for db13?db5 lsb switches refio fs adj dvdd dcom clock 3.3v r set 2k 0.1 f iouta ioutb AD9744 sleep latches i ref v refio clock ioutb iouta r load 50 v outb v outa r load 50 v diff = v outa ? v outb mode figure 3. simplified block diagram
rev. 0 AD9744 ?10? reference control amplifier the AD9744 contains a control amplifier that is used to regu- late the full-scale output current, i outfs . the control amplifier is configured as a v-i converter as shown in figure 4, so that its current output, i ref , is determined by the ratio of the v refio and an external resistor, r set , as stated in equation 4. i ref is copied to the segmented current sources with the proper scale factor to set i outfs as stated in equation 3. the control amplifier allows a wide (10:1) adjustment span of i outfs over a 2 ma to 20 ma range by setting i ref between 62.5 m a and 625 m a. the wide adjustment span of i outfs provides several benefits. the first relates directly to the power dissipa- tion of the AD9744, which is proportional to i outfs (refer to the power dissipation section). the second relates to the 20 db adjustment, which is useful for system gain control purposes. the small signal bandwidth of the reference control amplifier is approximately 500 khz and can be used for low-frequency small signal multiplying applications. dac transfer function both dacs in the AD9744 provide complementary current outputs, iouta and ioutb. iouta will provide a near full- scale current output, i outfs , when all bits are high (i.e., dac code = 16383), while ioutb, the complementary output, provides no current. the current output appearing at iouta and ioutb is a function of both the input code and i outfs and can be expressed as: iouta dac code i outfs = (/) 16384 (1) ioutb dac code i outfs = (e )/ 16383 16384 (2) where dac code = 0 to 16383 (i.e., decimal representation). as mentioned previously, i outfs is a function of the reference current i ref , which is nominally set by a reference voltage, v refio , and external resistor, r set . it can be expressed as: ii outfs ref = 32 (3) where iv r ref refio set = / (4) the two current outputs will typically drive a resistive load directly or via a transformer. if dc coupling is required, iouta and ioutb should be directly connected to matching resistive loads, r load , that are tied to analog common, acom. note, r load may represent the equivalent load resistance seen by iouta or ioutb as would be the case in a doubly terminated 50 w or 75 w cable. the single-ended voltage output appearing at the iouta and ioutb nodes is simply: v iouta r outa load = (5) v ioutb r outb load = (6) note the full-scale value of v outa and v outb should not exceed the specified output compliance range to maintain specified distortion and linearity performance. v iouta ioutb r diff load = (e) (7) substituting the values of iouta , ioutb , i ref , and v diff can be expressed as: v dac code rrv diff load set refio = {} () (e)/ / 2 16383 16384 32 (8) these last two equations highlight some of the advantages of operating the AD9744 differentially. first, the differential operation will help cancel common-mode error sources asso- ciated with iouta and ioutb , such as noise, distortion, and dc offsets. second, the differential code dependent current and subsequent voltage, v diff , is twice the value of the single- ended voltage output (i.e., v outa or v outb ), thus providing twice the signal power to the load. note, the gain drift temperature performance for a single-ended (v outa and v outb ) or differential output (v diff ) of the AD9744 can be enhanced by selecting temperature tracking resistors for r load and r set due to their ratiometric relationship as shown in equation 8. analog outputs the complementary current outputs in each dac, iouta and ioutb, may be configured for single-ended or differential opera- tion. iouta and ioutb can be converted into complementary single- ended voltage outputs, v outa and v outb , via a load resistor, r load , as described in the dac t ransfer function section by equations 5 through 8. the differential voltage, v diff , existing between v outa and v outb can also be converted to a single-ended voltage via a transformer or differential amplifier configuration. the ac performance of the AD9744 is optimum and specified using a differential transformer coupled output in which the voltage swing at iouta and ioutb is limited to 0.5 v. the distortion and noise performance of the AD9744 can be enhanced when it is configured for differential operation. the common-mode error sources of both iouta and ioutb can be significantly reduced by the common-mode rejection of a transformer or differential amplifier. these common-mode error sources include even-order distortion products and noise. the enhancement in distortion performance becomes more signifi- cant as the frequency content of the reconstructed waveform increases and/or its amplitude decreases. this is due to the first order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise. performing a differential-to-single-ended conversion via a trans- former also provides the ability to deliver twice the reconstructed signal power to the load (i.e., assuming no source termination). since the output currents of iouta and ioutb are comple- mentary, they become additive when processed differentially. a properly selected transformer will allow the AD9744 to provide the required power and voltage levels to different loads. the output impedance of iouta and ioutb is determined by the equivalent parallel combination of the pmos switches associated with the current sources and is typically 100 k w in parallel with 5 pf. it is also slightly dependent on the output voltage (i.e., v outa a nd v outb ) due to the nature of a pmos device. as a result, maintaining iouta and/or ioutb at a virtual ground via an i-v op amp configuration will result in the optimum dc linearity. note the inl/dnl specifications for the AD9744 are measured with iouta maintained at a virtual ground via an op amp.
rev. 0 AD9744 ?11? iouta and ioutb also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance. the negative output compliance range of e1.0 v is set by the breakdown limits of the cmos process. operation beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the AD9744. the positive output compliance range is slightly dependent on the full-scale output current, i outfs . it degrades slightly from its nominal 1.2 v for an i outfs = 20 ma to 1.0 v for an i outfs = 2 ma. the optimum distortion performance for a single-ended or differ- ential output is achieved when the maximum full-scale signal at iouta and ioutb does not exceed 0.5 v. digital inputs the AD9744?s digital section consists of 14 input bit channel and a clock input. the 14-bit parallel data inputs follow stan- dard positive binary coding where db13 is the most significant bit (msb) and db0 is the least significant bit (lsb). iouta produces a full-scale output current when all data bits are at logic 1. ioutb produces a complementary output with the full-scale current split between the two outputs as a function of the input code. dvdd digital input figure 6. equivalent digital input the digital interface is implemented using an edge-triggered master/slave latch. the dac output updates on the rising edge of the clock and is designed to support a clock rate as high as 165 msps. the clock can be operated at any duty cycle that meets the specified latch pulsewidth. the setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met, although the location of these transition edges may affect digital feedthrough and distortion performance. best performance is typically achieved when the input data transi- tions on the falling edge of a 50% duty cycle clock. dac timing input clock and data timing relationship dynamic performance in a dac is dependent on the relation- ship between the position of the clock edges and the point in time at which the input data changes. the AD9744 is rising edge triggered, and so exhibits dynamic performance sensitivity when the data transition is close to this edge. in general, the goal when applying the AD9744 is to make the data transition close to the falling clock edge. this becomes more im portant as the sample rate increases. figure 7 shows the relationship of sfdr to clock placement with different sample rates. note that at the lower sample rates, more tolerance is allowed in clock placement, while at higher rates, more care must be taken. ?3 ?2 2 ?1 0 1 70 80 time (ns) of data change relative to ri sing clock edge sfdr ? dbc 3 60 50 40 65 75 55 45 f out = 50mhz f out = 20mhz figure 7. sfdr vs. clock placement @ f out = 20 mhz and 50 mhz sleep mode operation the AD9744 has a power-down function that turns off the output current and reduces the supply current to less than 4 ma over the specified supply range of 3.0 v to 3.6 v and tempera- ture range. this mode can be activated by applying a logic level 1 to the sleep pin. the sleep pin logic threshold is equal to 0.5 avdd. this digital input also contains an active pull- down circuit that ensures the AD9744 remains enabled if this input is left disconnected. the AD9744 takes less than 50 ns to power down and approximately 5 m s to power back up. power dissipation the power dissipation, p d , of the AD9744 is dependent on several factors that include: the power supply voltages (avdd and dvdd) the full-scale current output i outfs the update rate f clock the reconstructed digital input waveform the power dissipation is directly proportional to the analog supply current, i avdd , and the digital supply current, i dvdd . i avdd is directly proportional to i outfs as shown in figure 8 and is insensitive to f clock . conversely, i dvdd is dependent on both the digital input waveform, f clock , and digital supply dvdd. figure 9 shows i dvdd as a function of full-scale sine wave output ratios (f out /f clock ) for various update rates with dvdd = 3.3 v.
rev. 0 AD9744 ?12? i outfs ? ma 35 0 2 i av d d ? ma 30 25 20 15 10 46810 12 14 16 18 20 figure 8. i avdd vs. i outfs ratio ? f out / f clock 16 0.01 1 0.1 i dvdd ? ma 14 12 10 8 6 4 2 0 165msps 125msps 65msps figure 9. i dvdd vs. ratio @ dvdd = 3.3 v applying the AD9744 output configurations the following sections illustrate some typical output configura- tions for the AD9744. unless otherwise noted, it is assumed that i outfs is set to a nominal 20 ma. for applications requir- ing the optimum dynamic performance, a differential output configuration is suggested. a differential output configuration may consist of either an rf transformer or a differential op amp configuration. the transformer configuration provides the opti- mum high-frequency performance and is recommended for any application that allows ac coupling. the differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain, and/or level shifting, within the bandwidth of the chosen op amp. a single-ended output is suitable for applications requiring a unipolar voltage output. a positive unipolar output voltage will result if iouta and/or ioutb is connected to an appropriately sized load resistor, r load , referred to acom . this configuration may be more suitable for a single-supply system requiring a dc-coupled, ground referred output voltage. alternatively, an amplifier could be configured as an i-v converter, thus converting iouta or ioutb into a negative unipolar voltage. this configuration provides the best dc linearity since iouta or ioutb is maintained at a virtual ground. differential coupling using a transformer an rf transformer can be used to perform a differential-to-single- ended signal conversion as shown in figure 10. a differentially coupled transformer output provides the optimum distortion per- formance for output signals whose spectral content lies within the transformer?s passband. an rf transformer, such as the mini- circuits t1e1t, provides excellent rejection of common-mode distortion (i.e., even-order harmonics) and noise over a wide fre quency range. it also provides electrical isolation and the ability to deliver twice the power to the load. transformers with different impedance ratios may also be used for impedance matching pur poses. note that the transformer provides ac coupling only. r load AD9744 22 21 mini-circuits t1-1t optional r diff iouta ioutb figure 10. differential output using a transformer the center tap on the primary side of the transformer must be connected to acom to provide the necessary dc current path for both iouta and ioutb. the complementary voltages appearing at iouta and ioutb (i.e., v outa and v outb ) swing symmetri- cally around acom and should be maintained with the specified output compliance range of the AD9744. a differential resistor, r diff , may be inserted in applications where the output of the transformer is connected to the load, r load , via a passive recon- struction filter or cable. r diff is determined by the transformer?s impedance ratio and provides the proper source termination that results in a low vswr. note that approximately half the signal power will be dissipated across r diff . differential coupling using an op amp an op amp can also be used to perform a differential-to-single-ended conversion as shown in figure 11. the AD9744 is configured with two equal load resistors, r load , of 25 w . the differential voltage developed across iouta and ioutb is converted to a single- ended signal via the differential op amp configuration. an optional capacitor can be installed across iouta and ioutb, forming a real pole in a low-pass filter. the addition of this capacitor also enhances the op amp?s distortion performance by preventing the dacs high slewing output from overloading the op amp?s input. AD9744 22 iouta ioutb 21 c opt 500 225 225 500 25 25 ad8047 figure 11. dc differential coupling using an op amp the common-mode rejection of this configuration is typically determined by the resistor matching. in this circuit, the differen- tial op amp circuit using the ad8047 is configured to provide some additional signal gain. the op amp must operate off of a dual supply since its output is approximately 1.0 v. a high- speed amplifier capable of preserving the differential performance
rev. 0 AD9744 ?13? of the AD9744 while meeting other system level objectives (i.e., cost, power) should be selected. the op amp?s differential gain, its gain setting resistor values, and full-scale output swing capa- bilities should all be considered when optimizing this circuit. the differential circuit shown in figure 12 provides the neces- sary level shifting required in a single-supply system. in this case, avdd, which is the positive analog supply for both the AD9744 and the op amp, is also used to level-shift the differ- ential output of the AD9744 to midsupply (i.e., avdd/2). the ad8041 is a suitable op amp for this application. AD9744 22 iouta ioutb 21 c opt 500 225 225 1k 25 25 ad8041 1k avdd figure 12. single supply dc differential coupled circuit single-ended unbuffered voltage output figure 13 shows the AD9744 configured to provide a unipolar output range of approximately 0 v to 0.5 v for a doubly termi- nated 50 w cable since the nominal full-scale current, i outfs , of 20 ma flows through the equivalent r load of 25 w . in this case, r load represents the equivalent load resistance seen by iouta or ioutb. the unused output (iouta or ioutb) can be connected to acom directly or via a matching r load . different values of i outfs and r load can be selected as long as the positive compliance range is adhered to. one additional consideration in this mode is the integral nonlinearity (inl) as discussed in the analog output section of this data sheet. for optimum inl performance, the single-ended, buffered voltage output configu- ration is suggested. AD9744 iouta ioutb 21 50 25 50 v outa = 0v to 0.5v i outfs = 20ma 22 figure 13. 0 v to 0.5 v unbuffered voltage output single-ended, buffered voltage output configuration figure 14 shows a buffered single-ended output configuration in which the op amp u1 performs an i-v conversion on the AD9744 output current. u1 maintains iouta (or ioutb) at a virtual ground, minimizing the nonlinear output impedance effect on the dac?s inl performance as discussed in the analog output section. although this single-ended configuration typically pro vides the best dc linearity performance, its ac distortion performance at higher dac update rates may be limited by u1?s slew rate capabilities. u1 provides a negative unipolar output voltage and its full-scale output voltage is simply the product of r fb and i outfs . the full-scale output should be set within u1?s voltage output swing capabilities by scaling i outfs and/or r fb . an improvement in ac distortion performance may result with a reduced i outfs since the signal current u1 will be required to sink less signal current. AD9744 22 iouta ioutb 21 c opt 200 u1 v out = i outfs r fb i outfs = 10ma r fb 200 figure 14. unipolar buffered voltage output power and grounding considerations, power supply rejection many applications seek high-speed and high-performance under less than ideal operating conditions. in these application circuits, the implementation and construction of the printed circuit board is as important as the circuit design. proper rf techniques must be used for device selection, placement, and routing as well as power supply bypassing and grounding to ensure optimum performance. figures 19 to 22 illustrate the recommended printed circuit board ground, power, and signal plane layouts that are implemented on the AD9744 evaluation board. one factor that can measurably affect system performance is the ability of the dac output to reject dc variations or ac noise superimposed on the analog or digital dc power distribution. this is referred to as the power supply rejection ratio. for dc variations of the power supply, the resulting performance of the dac directly corresponds to a gain error associated with the dac?s full-scale current, i outfs . ac noise on the dc supplies is common in applications where the power distribution is gener- ated by a switching power supply. typically, switching power supply noise will occur over the spectrum from tens of khz to several mhz. the psrr vs frequency of the AD9744 avdd supply over this frequency range is shown in figure 15. frequency ? mhz 85 40 12 6 0 psrr ? db 80 75 70 65 60 55 50 24 810 45 figure 15. power supply rejection ratio note that the units in figure 15 are given in units of (amps out/ volts in). noise on the analog power supply has the effect of modulating the internal switches, and therefore the output current. the voltage noise on avdd, therefore, will be added in a nonlinear manner to the desired iout. due to the relative different size of these switches, psrr is very code dep endent. this can produce a mixing effect that can modulate low-fre quency power supply noise to higher frequencies. worst-case psrr for
rev. 0 AD9744 ?14? either one of the differential dac outputs will occur when the full-scale current is directed toward that output. as a result, the psrr measurement in figure 15 represents a worst-case condition in which the digital inputs remain static and the full-scale output current of 20 ma is directed to the dac output being measured. an example serves to illustrate the effect of supply noise on the analog supply. suppose a switching regulator with a switching frequency of 250 khz produces 10 mv of noise and, for simplic- ity sake (i.e., ignore harmonics), all of this noise is concentrated at 250 khz. to calculate how much of this undesired noise will appear as current noise superimposed on the dac?s full-scale current, i outfs , one must determine the psrr in db using fi g ure 15 at 250 khz. to calculate the psrr for a given r load , such that the units of psrr are converted from a/v to v/v, adjust the curve in figure 15 by the scaling factor 20 l og(r load ). for instance, if r load is 50 w , the psrr is reduced by 34 db (i.e., psrr of the dac at 250 khz which is 85 db in figure 15 becomes 51 db v out /v in ). proper grounding and decoupling should be a primary objective in any high-speed, high resolution system. the AD9744 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. in general, avdd, the analog supply, should be decoupled to acom, the analog common, as close to the chip as physically possible. similarly, dvdd, the digital supply, should be decoupled to dcom as close to the chip as physically possible. for those applications that require a single 3.3 v supply for both the analog and digital supplies, a clean analog supply may be generated using the circuit shown in figure 16. the circuit consists of a differential lc filter with separate power supply and return lines. lower noise can be attained by using low esr type electrolytic and tantalum capacitors. 100 f elect. 0.1 f cer. ttl/cmos logic circuits 3.3v power supply ferrite beads avdd acom 10 f?22 f tant. figure 16. differential lc filter for single 3.3 v applications evaluation board general description the txdac family evaluation board allows for easy set up and testing of any txdac product in the 28-lead soic pack- age. careful attention to layout and circuit design combined with a prototyping area allow the user to evaluate the AD9744 easily and effectively in any application where high resolution, high-speed conversion is required. this board allows the user the flexibility to operate the AD9744 in various configurations. possible output configurations include transformer coupled, resistor terminated, and single and differ- ential outputs. the digital inputs are designed to be driven from various word generators, with the on-board option to add a resistor network for proper load termination. provisions are also made to operate the AD9744 with either the internal or external reference or to exercise the power-down feature.
rev. 0 AD9744 ?15? 2 r1 3 r2 4 r3 5 r4 6 r5 7 r6 8 r7 9 r8 10 r9 rp5 50 1 rcom 16 1 rp3 22 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db13x db12x db11x db10x db9x db8x db7x db6x db5x db4x db3x db2x db1x db0x 15 2 rp3 22 14 3 rp3 22 13 4 rp3 22 12 5 rp3 22 11 6 rp3 22 10 7 rp3 22 9 8 rp3 22 16 1 rp4 22 15 2 rp4 22 14 3 rp4 22 13 4 rp4 22 12 5 rp4 22 11 6 rp4 22 9 8 rp4 22 10 7 rp4 22 ckext ckextx 2 r1 3 r2 4 r3 5 r4 6 r5 7 r6 8 r7 9 r8 10 r9 rp6 50 1 rcom 2 r1 3 r2 4 r3 5 r4 6 r5 7 r6 8 r7 9 r8 10 r9 rp1 50 1 rcom 2 r1 3 r2 4 r3 5 r4 6 r5 7 r6 8 r7 9 r8 10 r9 rp2 50 1 rcom 21 db13x 4 3 db12x 65 db11x 87 db10x 10 9 db9x 12 11 db8x 14 13 db7x 16 15 db6x 18 17 db5x 20 19 db4x 22 21 db3x 24 23 db2x 26 25 db1x 28 27 db0x 30 29 32 31 34 33 ckextx 36 35 38 37 40 39 jp3 j1 ribbon tb1 1 tb1 2 l2 10 h c7 0.1 f tp4 blk + d vdd tp7 c6 0.1 f c4 10 f 25v blk blk tp8 tp2 red tb1 3 tb1 4 l3 10 h c9 0.1 f tp6 blk + a vdd tp10 c8 0.1 f c5 10 f 25v blk blk tp9 tp5 red figure 17. evaluation board: power supply and digital inputs
rev. 0 AD9744 ?16? r6 opt s2 iouta 2 a b jp10 1 3 ix r11 50 c13 10pf jp8 iout s3 4 5 6 3 2 1 t1 t1-1t jp9 c12 10pf r10 50 s1 ioutb 1 2 3 ab jp11 iy 1 ext 2 3 int ab jp5 ref + + c14 10 f 16v c16 0.1 f c17 0.1 f a vdd d vdd ckext db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 a vdd c15 10 f 16v c18 0.1 f c19 0.1 f cut under dut jp6 jp4 r5 10k d vdd r4 50 clock s5 clock tp1 wht d vdd a vdd d vdd r2 10k jp2 mode tp3 wht ref c2 0.1 f c1 0.1 f c11 0.1 f r1 2k 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 u1 AD9744 sleep tp11 wht r3 10k clock d vdd dcom mode a vdd reserved iouta ioutb acom nc fs adj refio reflo sleep db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 a vdd figure 18. evaluation board: output signal conditioning
rev. 0 AD9744 ?17? figure 19. primary side figure 20. secondary side
rev. 0 AD9744 ?18? figure 21. ground plane figure 22. power plane
rev. 0 AD9744 ?19? figure 23. assembly ? primary side figure 24. assembly ? secondary side
rev. 0 ?20? c02913?0?5/02(0) printed in u.s.a. AD9744 outline dimensions dimensions shown in inches and (mm) 28-lead standard small outline package (soic) (r-28) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) 45 0.7125 (18.10) 0.6969 (17.70) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 28 15 14 1 28-lead thin shrink so package (tssop) (ru-28) 28 15 14 1 0.386 (9.80) 0.378 (9.60) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0

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